GaN DHFET

ABSTRACT

The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising Al x Ga 1-x N. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional PatentApplication No. 60/475,545 filed Jun. 2, 2003, the disclosure of whichis hereby incorporated herein by reference.

FIELD

[0002] The present invention relates to a GaN-baseddouble-heterojunction field-effect transistor (DHFET) with improvedperformance characteristics. More specifically, the present inventionrelates to a GaN-based HFET comprising a buffer layer containing Al, anda channel layer, wherein the Al content in the buffer layer is relatedto the thickness of the channel layer.

BACKGROUND

[0003] Heterojunction field-effect transistors (HFETs) are commonly usedfor applications requiring low noise and high power. These transistorstypically contain a channel layer surrounded by a barrier layer and abuffer layer. Generally, there are two types of HFETs:single-heterojunction field-effect transistors (SHFETs) anddouble-heterojunction field-effect transistors (DHFETs). In SHFETs, thebuffer layer and channel layer are comprised of the same material, andthe barrier layer is comprised of a different material. Thechannel/barrier interface is the single heterojunction in thisstructure. In DHFETs the buffer layer and barrier layer are comprised ofdifferent materials than the channel layer. Thus, the buffer/channel andchannel/barrier interfaces are both heterojunctions. The key feature ofa HFET is that the channel/barrier heterojunction induces a highlyconductive, two-dimensional electron gas (2DEG) in the channel near theinterface.

[0004] Shown in FIG. 1 is a typical structure for a HFET. The HFETcomprises a substrate 1, and a nucleation layer 3. The substrate 1typically comprises GaN, AlGaN, SiC, diamond, sapphire, AlN, BN, orLiGaO₂. A buffer layer 5 is located on the nucleation layer 3 followedby a channel layer 7 and then a barrier layer 9. The nucleation layer 3provides a crystallographic transition between the substrate 1 and thebuffer layer 5, which may have different crystal structures. The channellayer 7 allows electrons in the channel to flow between the ohmic metalcontacts 13, which typically act as the source and drain of the HFET.

[0005] The barrier layer 9 induces a highly conductive, two-dimensionalelectron gas (2DEG) in the channel layer 7 near the interface with thebarrier layer 9 and also acts as an insulator between the gate 15 andthe channel layer 7. When electrons “spill” from the channel layer 7into the buffer layer 5, the performance of the transistor is reduced;thus, confinement of electrons in the channel layer 7 is highlydesirable. The barrier layer 9 is located on the channel layer 7. A caplayer 11 is also provided on a portion of the barrier layer 9. The caplayer 11 helps prevent oxide and other impurities from damaging thebarrier layer 9 during processing. Ohmic metal contacts 13 are alsoprovided. The ohmic contacts 13 are annealed at a high temperature suchthat they diffuse into the cap layer 11 and barrier layer 9, where theycontact the channel layer 7.

[0006] The following will describe some typical HFETs making referenceto the above description and the HFET structure shown in FIG. 1.GaN-based single-heterojunction field-effect transistors (SHFET) arecommonly used in the design of GaN HFETs. In a GaN-based SHFET thenucleation layer 3 comprises AlN or AlGaN. The buffer layer 5 comprisesGaN, the channel layer 7 comprises GaN, and the barrier layer 9comprises AlGaN. FIG. 2 is a band-edge diagram depicting the conductionband of a GaN-based SHFET where the buffer layer 5 comprises GaN, thechannel layer 7 comprises GaN and the barrier layer 9 comprisesAl_(0.28)Ga_(0.72)N. Because the bandgap of AlGaN is larger than that ofGaN, there is a band-edge discontinuity at the interface between thebarrier layer 9 and channel layer 7. The nature of this discontinuity issuch that a potential energy well for electrons is formed in the channellayer 7 near the barrier layer 9. Electrons are confined to the channellayer 7 and a 2DEG is formed. It is important to note that because AlGaNand GaN have different lattice parameters, the interface between thesematerials is strained. This strain results in positive polarizationcharges at the channel layer 7 and barrier layer 9 interface. Thesecharges intensify the sharp band-edge discontinuity at the interfacebetween the barrier layer 9 and channel layer 7, further confiningelectrons to the 2DEG. However, the interface between the channel layer7 and buffer layer 5 is not a heterointerface; thus there are nodifferences in bandgap or positive polarization charges and theconduction band is continuous. As a result, it is easy for so-called“hot electrons” to spill into the buffer layer 5 from the channel layer7. “Hot electrons” are electrons that have sufficient energy to escapethe attractive pull of the potential energy well at the interfacebetween the channel layer 7 and barrier layer 9. They are typicallypresent in high-electric field regions of the channel layer 7. The hotelectron effect occurs because electron energy-relaxation time istypically significantly longer than their momentum relaxation time.These electrons have sufficient energy to move into another region, suchas the buffer layer 5, ultimately degrading the performance of theSHFET.

[0007] The confinement of the 2DEG in the channel layer 7 can beimproved by using a double-heterojunction structure in which the bufferlayer 5 comprises a material having a wider bandgap than that of thechannel layer 7. For example, in InP-based HFETs (so called because thedevice layers are grown on InP substrates), double-heterojunction fieldeffect transistors (DHFETs) have been utilized. DHFETs are alsodiscussed in U.S. Pat. No. 4,827,320 and in Loi. D. Nguyen et al., IEEETransaction on Electron Devices, vol. 39, pp 2007-2014 (1992). Aband-edge diagram of an InP-based DHFET where the buffer layer 5comprises Al_(0.48)In_(0.52)As, the channel layer 7 comprisesIn_(0.53)Ga_(0.47)As and the barrier layer 9 comprisesAl_(0.48)In_(0.52)As is shown in FIG. 3. As can be seen, the sharpband-edge discontinuities which exist at the interface between thebarrier layer 9 and channel layer 7, as well as at the interface betweenthe channel layer 7 and buffer layer 5, help confine the 2DEG to thechannel layer 7. Similar results have also been attainable using otherwide-gap materials such as GaAs and narrower-gap materials such as InAs.However, InP-, GaAs- and InAs-based materials do not provide theadvantages of using GaN-based materials. For example, GaN-basedmaterials have much larger bandgaps than InP-, GaAs-, or InAs-basedtransistors which allow a higher voltage to be applied to the transistorbefore entering breakdown.

[0008] Designs for DHFETs implemented in GaN-based materials havemimicked designs for DHFETs implemented in InP-, GaAs-, and InAs-basedmaterials. One attempt at demonstrating such an analogous device isdiscussed in N. Maeda et al., physica status solidi (b) pp. 727-731(1999). Shown in FIG. 4 is a band-edge diagram of a GaN-based DHFET. Thebuffer layer 5 comprises Al_(0.095)Ga_(0.905)N, the channel layer 7comprises GaN and the channel layer 9 comprises Al_(0.28)Ga_(0.72)N. Ingeneral though, the buffer layer 5 comprises Al_(x)Ga_(1-x)N, thechannel layer 7 comprises GaN, and the barrier layer 9 comprises AlGaN,where x is typically in the range of 15%<x<50%. Such a structure isdiscussed in U.S. Pat. 5,929,467. This Al concentration yields an AlGaNalloy with a bandgap much larger than that of the GaN of the channellayer 7 (just as the bandgap of the Al_(0.48)In_(0.52)As buffer layer ismuch larger than that of the In_(0.53)Ga_(0.47)As channel layer inInP-based DHFETs). However, such attempts to mimic the 2DEG confinementin GaN, in a manner similar InP-, GaAs- and InAs-DHFETs have provenunsuccessful.

[0009] These GaN DHFETs contain large polarization charges at theinterface between the buffer layer 5 and channel layer 7. These chargesresult in exceptionally large electric fields at that interface whichcause the valence band edge on the channel layer 7 side to rise abovethe Fermi level at the interface, as shown in FIG. 4. As a result, atwo-dimensional hole gas (2DHG) forms at the interface of the channellayer 7 and buffer layer 5. The 2DHG increases the capacitance of theDHFET, which reduces the performance of the transistor. Furthermore, the2DHG is poorly controlled by the voltage at the gate 15, and becausehole mobility is significantly lower than electron mobility, thefrequency response of the DHFET is significantly limited.

[0010] As a result, there is a need for a HFET that provides the bandgapcharacteristics of GaN-based HFETs, confines the 2DEG to the channellayer, and reduces the 2DHG.

SUMMARY

[0011] In order to achieve the need outlined above, and according to oneaspect of this invention, there is provided a DHFET having a channellayer comprising GaN and a buffer layer comprising Al_(x)Ga_(1-x)N,where the Al content (i.e. x) is varied depending on the thickness ofthe channel layer. The Al content in the buffer layer is significantlylower than the previously thought optimal value. Reducing the Al contentused in the buffer layer also helps cause a misalignment between theconduction band and valence band associated with the channel layer andbuffer layer, which helps to reduce the 2DHG, thereby enhancing theperformance of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 shows a HFET according to the prior art.

[0013]FIG. 2 shows a band diagram of a GaN-based SHFET according to theprior art.

[0014]FIG. 3 shows a band diagram of an InP-based DHFET according to theprior art.

[0015]FIG. 4 shows a band diagram of a GaN-based DHFET according to theprior art.

[0016]FIGS. 5a-5 j depict the fabrication of the DHFET of the presentinvention.

[0017]FIG. 6 shows a graph of the relation between the Al content in thebuffer layer against the channel layer thickness.

[0018]FIG. 7 shows the band diagram of the DHFET according to thepresent invention.

[0019]FIG. 8 shows the band diagram of the DHFET according to thepresent invention.

[0020]FIG. 9 shows the I-V curve of a GaN DHFET fabricated according tothe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present invention will now be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein.

[0022] A preferred embodiment of the present invention will now bedescribed with reference to FIGS. 5a-5 j and 6-8, where a GaN basedDHFET having a substrate 101, nucleation layer 103, buffer layer 105,channel layer 107, barrier layer 109, and cap layer 111 is described.These layers can be made and deposited, for example, using molecularbeam epitaxy (MBE) technologies. The substrate 101, shown in FIG. 5a,may comprise GaN, AlGaN, SiC, diamond, sapphire, AlN, BN, or LiGaO₂. Anucleation layer 103 is preferably deposited on the substrate 101, asshown in FIG. 5b, and typically has a thickness in the range of 10-50nm. The nucleation layer 103 comprises AlN or AlGaN and preferably has a<0001> crystal structure. A buffer layer 105, shown in FIG. 5c, isdeposited on the nucleation layer 103, if used, or directly on thesubstrate 101. The buffer layer 105 preferably comprisesAl_(x)Ga_(1-x)N. The crystal structure of the nucleation layer 103, ifused, is provided so as to be able to form strong bonds with thesubstrate 101 and buffer layer 105. A channel layer 107 is deposited onthe buffer layer 105, as shown in FIG. 5d. The channel layer 107preferably comprises GaN, however InGaN can work equally as well. Also,the channel layer 107 preferably has a sheet charge (Ns) of 1×10⁻¹³cm⁻².

[0023] The buffer layer 105 helps prevent the 2DEG in the channel layer107 from spilling into the substrate 101 and the nucleation layer 103.The Al content (i.e. x) in the Al_(x)Ga_(1-x)N buffer layer 105 isdirectly dependent on the thickness of the channel layer 107, and willbe discussed later. A barrier layer 109 is deposited on the channellayer 107, as shown in FIG. 5e, to provide electrons to the channel 107.The barrier layer 109 also acts as an insulator between a subsequentlydeposited gate and the channel layer 107, and preferably comprises sixsublayers, sequentially deposited on top of each other, as shown in FIG.5f, having the following compositions:

[0024] First sublayer 109 a: 2 nm-10 nm thick layer of undopedAl_(0.3)Ga_(0.7)N;

[0025] Second sublayer 109 b: 2×10¹² cm¹² total sheet charge (planar ordelta) doped Al_(0.3)Ga_(0.7)N layer of a molecular layer to severalmolecular layers;

[0026] Third sublayer 109 c: 10 nm-28 nm thick layer of undopedAl_(0.3)Ga_(0.7)N;

[0027] Fourth sublayer 109 d: 10 nm thick, 1×10¹⁹ cm⁻³ dopedAl_(0.3)Ga_(0.7)N layer;

[0028] Fifth sublayer 109 e: 2×10¹³ cm⁻² total sheet charge (planar ordelta) doped Al_(0.3)Ga_(0.7)N layer; and

[0029] Sixth sublayer 109 f: 10 nm-30 nm thick compositionally gradedAl_(x)Ga_(1-x)N layer, wherein 0<x<0.3.

[0030] In order to calculate the optimal value of x for a given channellayer 107 thickness, a one-dimensional model for calculating GaN DHFETband diagrams that accounts for polarization charges at heterojunctioninterfaces was developed. The model is used to calculate the banddiagram of the DHFET by numerically solving a set of coupled Poisson andSchrödinger equations using AlGaN material parameters taken from O.Ambacher et al., Journal of Applied Physics 85, pp. 3222-3233 (1999).Using the model to analyze the failure of conventional GaN DHFETstructures, it was found that the high Al content used for the barrierand buffer layers in conventional GaN DHFET's resulted in a bandstructure similar to the one shown in FIG. 4 that fundamentally limitsdevice performance.

[0031] Using this model, a more optimal value of x (that is, thealuminum mole fraction in the buffer layer 105) versus the thickness ofthe channel layer 107, was calculated and will now be discussed withreference to FIGS. 6 and 7. FIG. 6 depicts a hatched region defined bycurve A, curve B, line C, and line D. Curve A is the upper limit of xvs. the channel layer 107 thickness and curve B is the lower limit of xvs. the channel layer 107 thickness. Curves A and B are comprised of aplurality of points, of which several are represented by Table 1 andshown in FIG. 6. For practical depiction only, those portions of curvesA and B defined for channel layer 107 thicknesses between 5 nm and 100nm are represented in Table 1 and shown in FIG. 6. TABLE 1 POINTS X (%)THICKNESS (nm) 1A 32 5 2A 8.5 20 3A 4 40 4A 2.8 60 5A 2 80 6A 1.6 100 1B8 5 2B 2 20 3B 1 40 4B 0.65 60 5B 0.52 80 6B 0.39 100

[0032] From Table 1 and graph 6, the shaded region can be defined as theregion contained by curve A, curve B, line C, and line D, wherein:

[0033] (A) curve A is a curve for smoothly connecting six points of 1A(the upper value of x for a channel layer thickness of 5 nm), 2A (theupper value of x for a channel layer thickness of 20 nm), 3A (the uppervalue of x for a channel layer thickness of 40 nm), 4A (the upper valueof x for a channel layer thickness of 60 nm), 5A (the upper value of xfor a channel layer thickness of 80 nm), 6A (the upper value of x for achannel layer thickness of 100 nm);

[0034] (B) curve B is a curve for smoothly connecting six points of 1B(the lower value of x for a channel layer thickness of 5 nm), 2B (thelower value of x for a channel layer thickness of 20 nm), 3B (the lowervalue of x for a channel layer thickness of 40 nm), 4B (the lower valueof x for a channel layer thickness of 60 nm), 5B (the lower value of xfor a channel layer thickness of 80 nm), 6B (the lower value of x for achannel layer thickness of 100 nm);

[0035] (C) line C is specified by a channel layer thickness of 5 nm; and

[0036] (D) line D is specified by a channel layer 107 thickness of 100nm.

[0037] The thickness of the channel layer 107 generally does not fallbelow 5 nm because the energy of the ground state of the 2DEG increasesrapidly as the channel layer 107 thickness is reduced below this value.In the limit of an infinitely thin channel layer 107, the ground staterises to the top of the channel layer 107, electrons are no longerconfined to the channel layer 107, and the 2DEG ceases to exist.

[0038] For purposes of comparison, FIG. 7 shows a calculated band-edgediagram using the aforementioned model. FIG. 7 is similar to theband-edge diagram for the GaN-based SHFET shown in FIG. 2. However, theband-edge diagram of FIG. 7 further includes three conduction bands fora GaN-based DHFET according to the present invention using threedifferent values for the Al content in the buffer layer 107. The threeconduction bands show Al contents (x) of 1%, 2%, and 3%, for a channellayer 107 having a thickness of 40 nm. At the first interface 106between the buffer layer 105 and the channel layer 107, there is adiscontinuity in the conduction band. More specifically, the portion ofthe conduction band defined by the buffer layer 105 at the firstinterface 106 is at a greater potential than the portion of theconduction band defined by the channel layer 107 at the first interface106. It is this discontinuity and the gradient in potential energythroughout the channel layer 107 that helps confine the 2DEG to thechannel layer 107. Similarly at the second interface 108 located betweenthe channel layer 107 and the barrier layer 109, a discontinuity in theconduction band exists. More specifically, the portion of the conductionband defined by the barrier layer 109 at the second interface 108 is ata higher potential than the portion of the conduction band defined bythe channel layer 107 at the second interface 108.

[0039]FIG. 8 is another calculated band-edge diagram of a GaN-basedDHFET with a channel layer thickness and Al content chosen in accordancewith the present invention. As can be seen, the channel layer 107 has athickness of 400 Å and the Al content of the Al_(x)Ga_(1-x)N in thebuffer layer is 4%. Also, the barrier layer comprisesAl_(0.28)Ga_(0.72)N. The conduction band is discontinuous at theinterface between the buffer layer and channel layer, and the portion ofthe conduction band in the buffer layer at the first interface is at agreater potential than the portion of the conduction band in the channellayer at the first interface. In addition, the valence band defined inthe channel layer 107 and buffer layer 105 at the first interface doesnot cross the Fermi level at the first interface which helps suppress a2DHG from forming.

[0040] Shown in FIG. 9 is an experimental I-V curve of a GaN DHFET and aGaN SHFET for increasing gate-source voltages, fabricated according tothe present invention. In the graph, the GaN DHFET has a channel layerwith a thickness of 40 nm, and a buffer layer with a composition ofAl_(0.02)Ga_(0.98)N. The x-axis represents the drain-source voltage (involts), and the y-axis represents the drain current (in Amps). The DHFETis depicted by the dark circles and the SHFET is depicted by the lightsquares. As can be seen in the graph, in the saturation region the I-Vcurve of the DHFET is substantially flat, while the I-V curve for theSHFET has a slight incline. As a result, the output conductance (i.e.the ratio of the change in drain current over the change in drain-sourcevoltage) will be lower for the GaN DHFET than for the SHFET. This is dueto improved confinement of hot electrons in the channel layer of the GaNDHFET.

[0041] Referring back to FIG. 5g, after the deposition of the barrierlayer 109, a cap layer 111 preferably comprising GaN is deposited. Thecap layer 111 helps prevent the surface of the barrier layer 109 frombeing damaged by oxide or other impurities. The cap layer 111 may alsobe heavily doped to facilitate the fabrication of ohmic contacts(discussed below). After the cap layer 111 is deposited, a layer ofphotoresist 113 is deposited, as shown in FIG. 5h. A portion of thephotoresist 113 is patterned and removed using UV lithography. Ohmicmetal contacts 115 are deposited in the region where the photoresist isremoved. The remaining photoresist is removed by soaking the DHFET in aphotoresist stripper for about 1 hour at about 100° C. and rinsing in DIwater. The ohmic contacts are annealed at a temperature between about600° C. and 900° C. in a nitrogen ambient for about 30 seconds, as shownin FIG. 5i. Annealing the ohmic metal contacts 115 allows them todiffuse into the structure such that they contact the channel layer 107.The ohmic metal contacts 115 may be deposited using any commerciallyavailable e-beam evaporator or similar device and can be used as thesource and drain of the HFET. The ohmic metal contacts 115 preferablycomprise a 20 nm layer of Ti, a 200 nm layer of Al, and another 100 nmlayer of Pt, deposited in that order. Optionally, after depositing theohmic metal contacts 115, a layer of SiN about 50 nm thick may bedeposited on a portion of the ohmic metal contacts 115 to prevent theohmic metal contacts 115 from moving during the annealing step. Thisoptional step is the subject matter of U.S. Ser. No. 60/401,414. If aplurality of HFET's are being fabricated on a wafer, they can now beseparated using either ion implantation or mesa etching.

[0042] Next, an opening for a gate is created. Using the ohmic contacts115 or the optional SiN layer as a mask, a portion of the cap layer 111is removed preferably using a reactive ion etch with a chlorine gas, ora wet chemical etch. A gate 119 preferably having a T-shaped structureis then deposited using bi-layer e-beam lithography on the barrier layer109, as shown in FIG. 5j. The gate 119 preferably comprises a 20 nmlayer of Pt, a 20 nm layer of Ti, and a 310 nm layer of Au, deposited inthat order. However, other metal combinations such as Ni/Au, Pt/Ti/Au,W/Ti/Au, W/Al, W/Ti/Au, W/Si/Al, W/Si/Ti/Au can be used equally as well.The gate 119 is passivated by surrounding the sides of the gate 119 (notthe gate surface) and the exposed part of the barrier layer 109 with adielectric such as silicon dioxide or silicon nitride.

[0043] Let it be understood that the foregoing description is onlyillustrative of the invention. Various alternatives and modificationscan be devised by those skilled in the art without departing from thespirit of the invention. Accordingly, the present invention is intendedto embrace all such alternatives, modifications, and variances whichfall within the scope of the appended claims.

What is claimed is:
 1. A heterostructure semiconductor device having: abuffer layer comprising Al_(x)Ga_(1-x)N, where x is in the range of 1%to 4%; and a channel layer disposed on the buffer layer, therebydefining a first interface located between the buffer layer and thechannel layer, the channel layer comprising GaN, and having a thicknessin the range of 40-100 nm.
 2. The heterostructure semiconductor deviceof claim 1, wherein the buffer layer and the channel layer each define aportion of a conduction band, the conduction band being discontinuous atthe first interface.
 3. The heterostructure semiconductor device ofclaim 2, further comprising a barrier layer disposed over the channellayer, wherein a second interface is defined between the barrier layerand the channel layer, and wherein the barrier layer defines a portionof the conduction band, the conduction band being discontinuous at thesecond interface.
 4. The heterostructure semiconductor device of claim2, wherein the portion of the conduction band defined by the bufferlayer at the first interface is at a greater potential than the portionof the conduction band defined by the channel layer at the firstinterface.
 5. The heterostructure semiconductor device of claim 3,wherein the portion of the conduction band defined by the barrier layerat the second interface is at a greater potential than the portion ofthe conduction band defined by the channel layer at the secondinterface.
 6. The heterostructure semiconductor device of claim 1,wherein the buffer layer and channel layer each define a portion of avalence band and a portion of a Fermi level, wherein the portion of thevalence band defined by the buffer layer at the first interface and theportion of the valence band defined by the channel layer at the firstinterface are at a potential lower than the Fermi level at the firstinterface.
 7. A heterostructure semiconductor device comprising: abuffer layer comprising Al_(x)Ga_(1-x)N; and a channel layer disposed onthe buffer layer, thereby defining a first interface located between thebuffer layer and channel layer, the channel layer comprising GaN;wherein the value of x falls within a range contained between a curve A,a curve B, a line C, and a line D in a graph showing a relation betweenthe value of x and the thickness of the channel layer, wherein: thecurve A smoothly connects six points of an upper x value of 32% at thechannel layer thickness of 5 nm, an upper x value of 8.5% for thechannel layer thickness of 20 nm, an upper x value of 4% for the channellayer thickness of 40 nm, an upper x value of 2.8% for the channel layerthickness of 60 nm, an upper x value of 2% for the channel layerthickness of 80 nm, an upper x value of 1.6% for the channel layerthickness of 100 nm; the curve B smoothly connects six points of a lowerx value of 8% for the channel layer thickness of 5 nm, a lower x valueof 2% for the channel layer thickness of 20 nm, a lower x value of 1%for the channel layer thickness of 40 nm, a lower x value of 0.65% forthe channel layer thickness of 60 nm, a lower x value of 0.52% for thechannel layer thickness of 80 nm, a lower x value of 0.39% for thechannel layer thickness of 100 nm; the line C is specified by thechannel layer thickness of 5 nm; and the line D is specified by thechannel layer thickness of 100 nm.
 8. The heterostructure semiconductordevice of claim 7, wherein the buffer layer and the channel layer eachdefine a portion of a conduction band, the conduction band beingdiscontinuous at the first interface.
 9. The heterostructuresemiconductor device of claim 8, further comprising a barrier layerdisposed over the channel layer, wherein a second interface is definedbetween the barrier layer and the channel layer, and wherein the barrierlayer defines a portion of the conduction band, the conduction bandbeing discontinuous at the second interface.
 10. The heterostructuresemiconductor device of claim 8, wherein the portion of the conductionband defined by the buffer layer at the first interface is at a greaterpotential than the portion of the conduction band defined by the channellayer at the first interface.
 11. The heterostructure semiconductordevice of claim 9, wherein the portion of the conduction band defined bythe barrier layer at the second interface is at a greater potential thanthe portion of the conduction band defined by the channel layer at thesecond interface.
 12. The heterostructure semiconductor device of claim7, wherein the buffer layer and channel layer each define a portion of avalence band and a portion of a Fermi level, wherein the portion of thevalence band defined by the buffer layer at the first interface and theportion of the valence band defined by the channel layer at the firstinterface are at a potential lower than the portion of the Fermi levelat the first interface.
 13. A heterostructure semiconductor devicecomprising: a buffer layer comprising Al_(x)Ga_(1-x)Ns; and a channellayer disposed on the buffer layer, thereby defining a first interfacelocated between the buffer layer and channel layer, the channel layercomprising GaN; a barrier layer disposed on the channel layer, therebydefining a second interface located between the barrier layer and thechannel layer, the barrier layer comprising AlGaN; a cap layer disposedon the barrier layer, the cap layer comprising GaN; ohmic metal contactsdeposited on the cap layer, wherein the ohmic metal contacts are incontact with the channel layer; a gate in contact with the barrierlayer; wherein the value of x and the thickness of the channel layerfall within a range surrounded by a curve A, a curve B, a line C, and aline D in a graph showing a relation between the value of x and thethickness of the channel layer, wherein: the curve A smoothly connectssix points of an upper x value of 32% at the channel layer thickness of5 nm, an upper x value of 8.5% for the channel layer thickness of 20 nm,an upper x value of 4% for the channel layer thickness of 40 nm, anupper x value of 2.8% for the channel layer thickness of 60 nm, an upperx value of 2% for the channel layer thickness of 80 nm, an upper x valueof 1.6% for the channel layer thickness of 100 nm; the curve B smoothlyconnects six points of a lower x value of 8% for the channel layerthickness of 5 nm, a lower x value of 2% for the channel layer thicknessof 20 nm, a lower x value of 1% for the channel layer thickness of 40nm, a lower x value of 0.65% for the channel layer thickness of 60 nm, alower x value of 0.52% for the channel layer thickness of 80 nm, a lowerx value of 0.39% for the channel layer thickness of 100 nm; the line Cis specified by the channel layer thickness of 5 nm; and the line D isspecified by the channel layer thickness of 100 nm.
 14. Theheterostructure semiconductor device of claim 13, wherein the bufferlayer, the channel layer, and the barrier layer each define a portion ofa conduction band, the conduction band being discontinuous at the firstinterface and the second interface.
 15. The heterostructuresemiconductor device of claim 14, wherein the portion of the conductionband defined by the buffer layer at the first interface is at a greaterpotential than the portion of the conduction band defined by the channellayer at the first interface.
 16. The heterostructure semiconductordevice of claim 14, wherein the portion of the conduction band definedby the barrier layer at the second interface is at a greater potentialthan the portion of the conduction band defined by the channel layer atthe second interface.
 17. The heterostructure semiconductor device ofclaim 13, wherein the buffer layer and channel layer each define aportion of a valence band and a portion of a Fermi level, wherein theportion of the valence band defined by the buffer layer at the firstinterface and the portion of the valence band defined by the channellayer at the first interface are at a potential lower than the Fermilevel at the first interface.
 18. A heterostructure semiconductor devicecomprising: a buffer layer; and a channel layer disposed on the bufferlayer, thereby defining a first interface located between the bufferlayer and the channel layer, the channel layer comprising a GaN; whereinthe buffer layer and channel layer define a portion of a conductionband, a valence band, and a Fermi level, and wherein the portion of theconduction band defined by the buffer layer at the first interface is ata greater potential than the portion of the conduction band defined bythe channel layer at the first interface; and wherein the portion of thevalence band defined by the buffer layer at the first interface and theportion of the valence band defined by the channel layer at the firstinterface are at a potential lower than the Fermi level at the firstinterface.
 19. The heterostructure semiconductor device of claim 18,further comprising a barrier layer disposed over the channel layer,wherein a second interface is defined between the barrier layer and thechannel layer, and wherein the barrier layer defines a portion of theconduction band, the portion of the conduction band defined by thebarrier layer at the second interface being at a greater potential thanthe portion of the conduction layer defined by the channel layer at thesecond interface.